1. Field of the Invention
This invention relates to electronic design automation tools and, more particularly, to pessimism reduction in timing and path delay analysis.
2. Description of the Related Art
During the design of an integrated circuit (IC), an automated design tool may be used to create the IC. The design flow includes a number of steps including schematic capture, circuit simulation, netlist creation, circuit layout, and others. In addition, to identify potential timing problems in the circuit, timing analysis is performed on the netlist. More particularly, the time that it takes signals such as clocks and data to propagate along a given path from a source to a destination is referred to as the path delay. Depending on parameters such as process, voltage, and temperature (PVT) the path delay may vary. There are a variety of ways of performing timing analysis. For example, static timing analysis and statistical timing analysis are both commonly used.
In an effort to identify potential worst-case path delays, timing models may use exhaustive searches of all possible parameter combinations. Alternatively, bounding methods may be used. In the bounding methods, the late delays and arrival times assuming the slowest possible conditions while assuming the fastest conditions for early delays and arrival times. While the bounding methods may provide a worst-case coverage, the analyses may provide overly pessimistic results.
Accordingly, there are conventional ways to reduce or remove pessimism from the timing analysis results, particularly in common paths. This removal process is sometimes referred to as common path pessimism removal (CPPR) or common reconvergent pessimism removal (CRPR). These methods typically remove or reduce PVT variation that has been added onto the gate delays in a clock path during analysis. For example, a timing path whose source and destination clock paths share common clock buffers may receive pessimism reduction by removing or reducing the PVT variation.
However, conventional tools that implement CPPR methods are restricted to correcting rising-edge-to-rising-edge, or falling-edge-to-falling-edge paths. For these types of paths, the pessimism removal process is straightforward. In contrast, circuits that use half-cycle clocking in which the timing path is rising-edge to falling-edge or vice versa, do not receive CPPR benefits, which can result in overly pessimistic timing. For example, in a half-cycle path, every picosecond (ps) of extra skew in the clocks may penalize the path slack by 2 ps. Thus, for circuits that contain a large number of logic levels (e.g., 20 or more levels), conventional CPPR tools may create a very pessimistic analysis.